I. SuperSpeed USB Interface

USB 3.0 era has just begun.

USB 3.0 standard is developed by Intel and HP, NEC, NXP, Microsoft and Texas Instruments, USB 3.0 goal is to provide ten times of bandwidth than the current, using new added two pairs of high-speed lines opens "Superspeed" mode, it can achieve about 4.8 Gbit / s, and may use optical fiber connection.

The USB 3.0 Technical specification was released on August 13, 2008, and its commercial products were released in 2009 or 2010. USB 3.0 added 5 contacts, two for the data output, two for data input, using the send list segment for data packet, the new contacts will be placed side by side in the rear of current four contacts. USB 3.0 tentative power supply standard is 900mA, it will support fiber optic transmission. USB 3.0 is designed to be compatible with USB 2.0 and USB 1.1, and uses more efficient protocols to conserve energy.

So why USB 3.0 has such a magical charm, how does it work?

II. USB 3.0 Specifications Analysis

Many people see the USB technology, only the interface and cable, but few people care about the data is in what form to be transmitted and processed in the USB interface. In today's desktops and laptops, as the host computer, they all contain the host controller. This small chip has a series of logical channels, which is responsible for managing various data transmission between host and devices. The current Hi-Speed USB interface, that is USB 2.0 interface, is used in a half-duplex structure, that is, data transmission is only unidirectional. First, peripheral device sends a signal to the computer, and then signal is sent by the computer to the peripheral device, both do not transfer information at the same time.

In the USB 3.0 specification, it will have its own dedicated data path, dedicated data transmission lines and independent data receiving lines. Therefore, in the time of data communication between the host and peripheral, you can truly achieve full-duplex. Both the host and the peripheral can send and receive data at the same time.

In addition the data transmission rate will also be greatly improved, can achieve 5Gb / s data transmission capacity, each direction can achieve 4.7Gb / s data throughput. At present, the fastest USB 2.0 specification can only achieve 480Mb / s by one-way.

Whether the host or the peripheral, all data transfers can occur at the same time, these dedicated data transceiver channels can reduce the data turnaround time to a minimum, and they can simultaneously issue operational requests. USB 3.0 interface backward compatible with previous USB 2.0 and USB1.1 interface.

III. USB 3.0 Pin / Contact Analysis

In order to backward compatible with USB 2.0 specification, but also greatly improve their bandwidth, USB 3.0 set up two sets of data transmission mechanism in a cable. One is convenient for the common USB 2.0 interface, the other is dedicated to send and receive high-speed transmission channel.

As shown, this is the USB 3.0 Micro B interface, pin 1 is for power supply (VBUS), pin 2 is USB 2.0 data -, pin 3 is USB 2.0 data +, pin 4 is USB On-The-Go ID, Pin 5 is the ground (GND), pin 6 is the USB 3.0 send data line -, pin 7 is USB 3.0 send data line +, pin 8 is the ground (GND), pin 9 is USB 3.0 Receive data line -, pin 10 is USB 3.0 receive data line +.

USB 3.0 Micro B

Leads of USB 3.0 including standard A / standard B / Micro Series are defined as follows:

Form 1   USB3.0 standard A /standard B/Micro B Pin Definition

IV. USB 3.0 Signal Integrity

Making a signal integrity requirement contrast between USB 3.0 and USB 2.0, USB 3.0 signal integrity specification is much higher than USB 2.0, see Table 2. You can also refer to the SuperSpeed Electrical Requirements of USB 3.0 specification 5.6.1.

Form 2  USB3.0 Signal Integrity

 In current, from the view of USB 3.0 cable design, high-frequency signal analysis and test results from various connector manufacturers, the Near-end Crosstalk and Differential to Common Mode Conversion are difficult to meet the specification requirements, and it needs improving signal integrity performance by further simulation analysis.